A NAND-type flash memory in which multiple memory cells are connected in series to form NAND strings has attracted an attention as one of non-volatile semiconductor memory devices capable of high integration. The memory cells of the NAND-type flash memory each have a MOSFET structure formed by stacking an electric charge accumulating layer (floating gate) and a control gate on a semiconductor substrate. In addition, each memory cell stores data “0” or “1” therein, depending on an amount of charges accumulated in the floating gate of the memory cell. Hereinafter, a state in which a threshold voltage of a transistor in a memory cell (hereinafter, referred to as a memory cell transistor) is positive is referred to as data “0” (programmed state), while a state in which the threshold voltage is negative is referred to as data “1” (erased state).
The data is programmed to the NAND-type flash memory by using a tunnel current of a memory cell transistor. Thus, the programming speed varies among memory cell transistors due to variation in manufacturing the memory cells, or other factors. Accordingly, even though the programming voltage and the programming time are the same for each of the memory cells, threshold voltages of the memory cell transistors programmed based on data “0” distribute in a certain range.
In order to employ a multi-level cell technology of storing data of two bits or more in a single memory cell for the purpose of achieving the NAND-type flash memory with a large capacity, it is necessary to check expansion of the range of the threshold distribution of the data levels of the memory cell transistors.
To meet the demand, there is proposed a method in which programming is performed on a memory cell until the bit line voltage reaches a threshold voltage lower than a desired threshold voltage (first programming), and then programming is further performed with the bit line voltage increased (second programming) (refer to Japanese Patent Laid Open (Kokai) 2004-23044). According to this method, the potential of a channel portion of a memory cell is increased by making the bit line voltage in the second programming higher than the bit line voltage in the first programming. Thereby, an electric field between the channel portion and the floating gate is alleviated, so that “weak” programming is performed. This achieves a narrower threshold voltage distribution. Here, the “weak” programming means programming in which a smaller amount of electrons are injected into the floating gate than that in an ordinary programming condition. The amount is smaller, for such a reason that an electric field between a channel portion and a floating gate is alleviated, or an application time period of programming pulses is shortened.
The method, however, has the following problem. Specifically, increasing the bit line voltage causes application of a reverse bias voltage to a junction of a contact portion of the bit line, and thus a junction leakage current is increased. Thereby, power consumption might be increased.